1. Field
The present disclosure is applicable to electronic integrated circuits (“ICs”), and particularly to level shifter circuits that convert binary signals from one voltage range to a different voltage range.
2. Related Art
It is usually desirable for an IC to operate from a single voltage supply. However, many ICs require two or more different voltage supplies internally for ideal operation. In such circumstances a binary-level signal that operates satisfactorily within the bounds of a first supply often needs to be conditioned so that it is capable of controlling circuits that operate across a different, typically wider, voltage range. Ideally, circuits are available that accept a logic level input signal to control one or more outputs that each range from the most positive voltage of a first, higher supply voltage to the lowest (or most negative) voltage of a second, lower supply voltage. In this paper, such circuits are referred to as “level shifters”. The logic level signal range need not be identical to either the higher or the lower supply voltage.
FIG. 1 illustrates an example of a level shifter that responds to a logic level input to control a circuit operating over a wider voltage range than that of the logic supply. The circuit operating over a wider voltage range is a relatively simple RF switch. A differential output level shifter 800 accepts a “Select A/B” input signal 102 that operates between logic+ and logic−. Both level shifter outputs switch between the positive supply, VDD 104, and the negative supply, VSS 106, depending on the voltage of the input 102. If the input 102 is high then OUT 108 will be driven to approximately VDD, while OUTX 110 will be driven to approximately VSS.
The voltages of the logic supply, and of VDD 104 and VSS 106, depend on the requirements of the circuit in which the level shifter operates. VDD and VSS supplies are often symmetric, having the same magnitude voltage. The exemplary embodiment described in the most detail herein is suitable for symmetric positive and negative supplies, but is also suitable for asymmetric supplies. As one example, logic+ and VDD 106 may both have a value of approximately 2.4V with respect to circuit common, which in turn may be approximately equal in potential to an RF reference voltage “ground” 140. VSS 106 may be −3.4V with respect to ground 112.
In other circuits the supply values may vary widely. As a first representative alternative, VDD may be +10V, logic+ +3V, logic− 0V, and VSS −10V. As a second representative alternative, VDD may be +6V, VSS may be −5V, and logic+ may be 0V while logic− is −5V. In a third alternative, VDD may be 2.4V, logic+ may be 2.4V, logic− may be 0 or common, and VSS may be −2.4V. The input control voltage range need not extend to either VDD or VSS. Indeed, though it is typically so, 0V or the “common” voltage disposed between VDD and VSS need not constitute either logic+ or logic−.
In the exemplary circuit of FIG. 1 the outputs OUT 108 and OUTX 110 control an SPDT (single pole double throw) RF switch to connect an antenna 114 to either an RF input A 116, or to an RF transmit signal B 118. When Select A/B 102 is high (or, more generally, “true”), the level shifter output OUT 108 is driven to about VDD, turning on FETs M1 120 and M2 122. The level shifter inverted output OUTX 110 is concurrently driven to VSS, turning off FETs M3 124 and M4 126. Consequently, the antenna 114 is coupled via FET M2 122 to input A 116 of a low noise amplifier (LNA) 128, which provides an amplified signal to RF Rcv 130 which is coupled to further receive processing circuits (not shown).
An RF signal intended for transmission may be provided to RF input 132 of a power amplifier 134, the output of which is matched to the impedance of the antenna 114 by a matching network 136. The matching network typically includes a blocking capacitor or other mechanism such that the RF transmit signal B 118 has a large amplitude RF signal with a mean voltage of zero volts. The RF Xmt input 132 should be quiescent when Select A/B 102 is true. In this “A” selection condition, FET M3 124 is off, while FET M1 120 shunts any residual signal present at B 118 to ground 112, thus minimizing interference with the extremely small RF receive signal picked up by the antenna 114.
When Select A/B 102 is false, OUT 108 is driven to VSS and OUTX 110 is driven to VDD. This causes FETs M3 124 and M4 126 to be turned on, and FETs M1 120 and M2 122 to be turned off. Accordingly, the RF transmit signal A 118 is no longer shunted to ground by M1 120, but instead is coupled to the antenna 114. The sensitive input to the LNA 128 is protected by M2 122 having a high impedance, plus M4 126 shunting any leakage signal to ground 112. Gate resistors (not shown) in series with the gate of each of M1-M4, in conjunction with parasitic drain-gate and gate-source capacitances Cdg and Cgs, protect the FETs from suffering excess voltages from gate to drain or source (Vgs and Vgd) because of the high frequency of the zero-average RF signal at B 118.
FIG. 1 illustrates an exemplary use of a level shifter to provide drive control to an RF signal switch circuit. The voltages VDD and VSS may be adjusted to the requirements of the FET switches, which often operate at much higher voltages than those employed for select signal Select A/B 102. The FETs of the RF SPDT switch may be high voltage devices, or may be low voltage devices arranged in a “stacked” or multiple-gate configuration that increases the overall voltage withstand capability of the switch. Of course, though FIG. 1 illustrates only one type of use for level shifter circuits such as level shifter 800, level shifters are employed in myriads of different types of circuits. Level shifters are thus highly useful for a wide range of purposes.
A method and apparatus having improved features for level shifting are described herein. The maximum operating voltage of a level shifter depends in part on the characteristics of the semiconductor process by which it is fabricated. However, circuit switching details may cause voltages to appear across devices, such as FETs, that have a transient value that is greater than the static voltages of the circuit. Such excessive voltages, even though transient, may eventually cause the level shifter circuit to fail even if they are too small to cause apparent harm for some time.
Among other useful features, the method and apparatus described herein include features that avoid such excessive transient voltages across semiconductor devices of a level shifter. This enables a given semiconductor process to control higher voltage and power, resulting in more cost-effective and reliable level shifters. Various aspects of the method and apparatus described herein will be seen to provide further advantages, as well.